Cornelis Networks, Inc.: Switch ASIC Design Engineer

remote-job.net Job Summary: 💶 Salary: Not specified ⏰ Weekly working hours: Full-time 🔍 Recommended experience: Senior 🎓 Recommended education: B.Sc. or M.Sc. in Computer Engineering, Electrical Engineering, or a related field 🏭 Industry: Semiconductors 📋 Key responsibilities: RTL design and latency optimization for core components of Switch ASICs. Microarchitecture specification for high-speed packet processing. Post-silicon validation and cross-system debugging. ✅ Key requirements: 10+ years of experience in digital design with Verilog/SystemVerilog. Experience with Ethernet/NoC/Crossbar/ASIC design for low-latency applications. Degree in Computer Engineering or Electrical Engineering (B.Sc./M.Sc.). About the company Cornelis Networks delivers high-performance, scalable networking solutions for AI and HPC data centers. The proprietary architecture integrates hardware, software, and system technologies to maximize the efficiency of GPU-, CPU-, and accelerator-powered clusters. The company is growing, with an international team of architects, engineers, and business professionals, backed by leading venture capital and strategic investors. Cornelis Networks hires for on-site, hybrid, and fully remote roles. Currently, experienced Senior ASIC Design Engineers are sought to contribute to the development of Switch ASICs for high-performance computing, data analytics, and AI interconnects. Responsibilities Design and implementation of core components for next-generation Ethernet Switch ASICs with a focus on RTL development and latency optimization. Creation of microarchitecture specifications for fast transmit/receive packet processing subsystems. Implementation of RTL in Verilog/SystemVerilog for low-latency data paths (including NoC and crossbar designs). Definition of timing constraints and collaboration with physical design engineers for timing optimization. Development of block- and system-level test plans in collaboration with verification teams. Support for post-silicon validation and debugging in coordination with hardware, firmware, and software teams. Contributions to performance optimization and energy-efficient design strategies for switch subsystems. Requirements B.Sc. or M.Sc. in Computer Engineering, Electrical Engineering, or a related field. At least 10+ years of professional experience in digital design with fluent application of Verilog and SystemVerilog (ideally 15+ years in total ASIC design). Deep knowledge of Ethernet architecture and network protocols (50G/100G/400G MAC/PCS, TCP/IP, RDMA/RoCE, IPSec). Experience with NoC or crossbar designs, Ethernet switch ASICs, and system debugging. Familiarity with timing closure and modern physical design methodologies. Experience in system-level debugging and root cause analysis; strong verbal and written communication skills. Desirable: Expertise in multi-clock-domain designs, scripting skills (TCL, Python, Perl), and experience with EDA tools (Design Compiler, Spyglass, PrimeTime). Benefits Competitive compensation package including base salary, equity, and variable incentives. Comprehensive health coverage (medical, dental, vision), as well as disability and life insurance. Additional perks such as dependent care FSA, accident insurance, and pet insurance. Generous paid holidays, Open Time Off (OTO) for full-time exempt employees, as well as sick days, parental leave, and maternity leave. 401(k) with company match (US standard) and performance/bonus opportunities. Flexible work models, including remote options (for employees in the US).