Cornelis Networks, Inc.: Ethernet Host Adaptor ASIC Design Engineer

remote-job.net Job summary: Salary: not specified Weekly hours: Full-time Recommended experience: Senior Recommended education: B.Sc. or M.Sc. in Computer Engineering, Electrical Engineering or a related field Industry: Semiconductor Main responsibilities: Development of microarchitectures and specifications for packet processors and high-speed data paths. Implementation of RTL in Verilog/SystemVerilog for host Ethernet adapters and data paths. Collaboration with verification and Physical Design teams on test coverage, timing closure and post-silicon debugging. Main requirements: Several years of experience in digital ASIC design with confident use of Verilog/SystemVerilog (minimum 7 years, ideally 10+–15+ years). Experience with RTL design for high-speed data paths and deep understanding of host Ethernet adapter architectures. Experience with timing closure, system-level debugging and familiarity with relevant EDA tools/scripting (desirable). About the company: Cornelis Networks delivers high-performance scale-out networking solutions for AI and HPC data centers. The architecture integrates hardware, software and system technologies to maximize the efficiency of GPU, CPU and accelerator clusters. The company is backed by leading venture capital and strategic investors and focuses on innovation, performance and scalability for demanding computing workloads. The team is rapidly growing, made up of architects, engineers and professionals, and is globally present across multiple U.S. states and six countries. Cornelis Networks hires on-site, hybrid and fully remote. Position focus: The advertised position is aimed at experienced Senior ASIC Design Engineers to develop SoCs for high-performance computing, data analytics and AI interconnect solutions. Responsibilities: Develop microarchitecture specifications for packet processors and high‑clocked, pipelined data paths with a focus on low latency. Implement RTL designs in Verilog/SystemVerilog for high-speed data paths and packet processing. Create block- and system-level test plans in collaboration with verification engineers. Define timing constraints and work with Physical Design engineers to optimize timing. Support post-silicon validation and debugging in collaboration with hardware, firmware and software teams. Contribute to performance optimization and energy-efficient design strategies for host-fabric interface subsystems. Requirements: B.Sc. or M.Sc. in Computer Engineering, Electrical Engineering or a related field. Several years of digital design experience; the job description indicates up to 15+ years of ASIC design experience (minimum 7 years post-college experience) and 10+ years of relevant experience in network hardware design. Strong knowledge of Verilog and SystemVerilog and experience with RTL design for high-speed data paths and packet processing. Deep understanding of host Ethernet adapter architectures as well as experience with timing closure and modern Physical Design methods. Experience in system-level debugging and root-cause analysis; strong verbal and written communication skills. Nice to have: Knowledge of Ethernet architectures/protocols (50G/100G/400G, TCP/IP, RDMA/RoCE, IPSec), multi-clock-domain designs, scripting languages (TCL, Python, Perl) and EDA tools (Design Compiler, Spyglass, PrimeTime). Benefits: Competitive compensation package with base salary, equity and performance-based incentives. Health, dental and vision insurance as well as disability and life insurance. 401(k) plan with employer matching (U.S. specification). Paid holidays, Open Time Off (OTO) for regular full-time employees, sick leave and other paid leaves (e.g., parental leave, pregnancy disability). Additional benefits such as Dependent Care FSA, accident insurance and pet insurance.