Cornelis Networks, Inc.: PCIe ASIC Design Engineer

remote-job.net Job Summary: 💶 Salary: not specified ⏰ Weekly hours: 40h 🔍 Recommended experience: Senior 🎓 Recommended education: Master in Electrical Engineering or Computer Engineering (or equivalent) 🏭 Industry: Semiconductor 📋 Main tasks: Integration of PCIe-IP into ASIC designs (end-to-end). Silicon bring-up and validation of PCIe links in the lab. Performance optimization and debugging of PCIe subsystems. ✅ Main requirements: 10+ years of experience in ASIC/SoC design with a focus on PCIe. Practical experience in silicon bring-up and debugging of high-speed interfaces. Deep knowledge of the PCIe protocol stack and scripting (e.g., Python/TCL). About the company: Cornelis Networks delivers high-performance, scalable networking solutions for AI and HPC datacenters. The architecture integrates hardware, software and system technologies to maximize the efficiency of GPU, CPU and accelerator clusters. We are a fast-growing, international team of architects, engineers and business professionals based in multiple U.S. states and six countries. We hire for on-site, hybrid and fully remote roles. Cornelis Networks is backed by leading venture capital and strategic investors and focuses on innovation, performance and scalability for demanding compute workloads. Responsibilities: End-to-end integration of PCIe-IP into complex ASIC designs. Lead silicon bring-up, validation and debugging of PCIe links in the lab. Collaborate with IP vendors, architecture, verification, physical design and software teams. Performance optimization across PHY, DMA and transaction layers. Contribute to system and microarchitecture with a focus on IO and interconnect scalability. Mentor junior engineers and define best practices for PCIe subsystems. Requirements: BS/MS in Electrical Engineering, Computer Engineering or comparable qualification. Over 10 years of industry experience in ASIC/SoC design with a focus on PCIe controller integration. Experience with silicon bring-up, debugging and validation of high-frequency interfaces. Deep understanding of the PCIe protocol stack (PHY, MAC, TLP, DLL), configuration space and link training. Experience with verification environments, performance tuning and power-aware design; familiarity with tools like VCS/Questa and lab equipment (protocol analyzers, oscilloscopes). Strong scripting skills (Python, Perl, TCL) and good communication skills. Desirable: Experience with PCIe Gen5/Gen6, retimer/switch solutions, CXL/CCIX, emulation and prototyping platforms (e.g., ZeBu, Palladium, HAPS) and a background in datacenter/AI-accelerator architectures. Benefits: Competitive compensation package consisting of base salary, equity, cash and incentives. Health, dental and vision insurance as well as disability and life insurance. 401(k) with company match (US-specific), Open Time Off (OTO) and additional paid leave. Flexible work models (including remote), generous holidays, sick days, parental and caregiver leave. Access to lab equipment and collaboration with leading names in the semiconductor industry.