2026 Graduate Machine Learning Engineer – Applied AI
Greenhouse
G
Hardware Development Engineer
<p class="paragraph"><span data-teams="true">At Graphcore, we’re building the future of AI compute.We’re a team of semiconductor, software and AI experts, with deep experience in creating the complete AI compute stack - from silicon and software to infrastructure at datacenter scale.As part of the SoftBank Group, backed by significant long-term investment, we are delivering key technology into the fast-growing SoftBank AI ecosystem.To meet the vast and exciting AI opportunity, Graphcore is expanding its teams around the world.We are bringing together the brightest minds to solve the toughest problems, in a place where everyone has the opportunity to make an impact on the company, our products and the future of artificial intelligence.</span></p>
<p><span data-contrast="auto">As a hardware development engineer you will analyse system requirements and design circuit solutions, in collaboration with Graphcore’s Silicon, Architecture and Software Teams.</span> <span data-contrast="auto">You will generate schematics and PCB layout constraints and work closely with the PCB CAD team to realise the designs. You will define test and validation plans, run test campaigns, report results, work closely with the firmware and system architecture teams to interpret results, debug and improve performance. </span><span data-ccp-props="{}"> </span></p>
<p><span data-ccp-props="{}"> </span></p>
<p><span data-contrast="auto">You will be expert in microprocessor system design and debug, with a deep understanding of processor power supply, reset & clocking requirements, memory, communications and control interfaces.</span><span data-ccp-props="{}"> </span></p>
<p><span data-ccp-props="{}"> </span></p>
<p><strong><span data-contrast="auto">The Team</span></strong><span data-ccp-props="{}"> </span></p>
<p><span data-contrast="auto">Graphcore’s Hardware Engineering Team creates both products for sale in volume production and hardware test & validation systems based on Graphcore’s IPU processor. These systems allow Graphcore’s customers to develop leading-edge machine-learning solutions for training and inference.</span><span data-ccp-props="{}"> </span></p>
<p><span data-ccp-props="{}"> </span></p>
<p class="paragraph"><span class="normaltextrun"><strong><span lang="EN-GB">What you’ll be doing</span></strong></span><span class="eop"><span lang="EN-GB"> </span></span></p>
<p><span data-contrast="auto">Development of production systems and test boards for Graphcore’s family of processors which includes:</span><span data-ccp-props="{}"> </span></p>
<p> </p>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="5" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="1" data-aria-level="1"><span data-contrast="auto">Circuit design, requirements analysis, functional definition, and component selection</span><span data-ccp-props="{}"> </span></li>
</ul>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="5" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="2" data-aria-level="1"><span data-contrast="auto">PCB Layout constraint definition, and support of PCB CAD layout team</span><span data-ccp-props="{}"> </span></li>
</ul>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="5" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="3" data-aria-level="1"><span data-contrast="auto">Circuit validation and verification</span><span data-ccp-props="{}"> </span></li>
</ul>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="5" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="4" data-aria-level="1"><span data-contrast="auto">Design and running of tests to validate circuit performance and margin</span><span data-ccp-props="{}"> </span></li>
</ul>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="5" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="5" data-aria-level="1"><span data-contrast="auto">Debugging and optimisation, in collaboration with the firmware team, of the correct system performance of microcontroller hardware control code</span><span data-ccp-props="{}"> </span></li>
</ul>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="5" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="6" data-aria-level="1"><span data-contrast="auto">Prototype production support, prototype bringup, evaluation & system test, prototype validation.</span><span data-ccp-props="{}"> </span></li>
</ul>
<ul>
<li data-leveltext="" data-font="Symbol" data-listid="5" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="7" data-aria-level="1"><span data-contrast="auto">Support of transfer to mass production.</span> <br><span data-ccp-props="{}"> </span></li>
</ul>
<p> </p>
<p><strong><span data-contrast="none"><span class="normaltextrun">What you’ll bring</span><span class="eop"><span lang="EN-GB"> </span></span><span lang="EN-GB"><br></span><span lang="EN-GB"><br></span><span lang="EN-GB">We appreciate not everyone will meet all of the criteria. If you meet most of the requirements below and believe you can bring value to this role, we’d love to hear from you.</span></span></strong></p>
<ul>
<li data-leveltext="·" data-font="Symbol" data-listid="6" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"·","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1"><span data-contrast="auto">Knowledge of DCDC voltage (including multi-phase) regulators, linear regulators and PCB design requirements for efficient power delivery</span><span data-ccp-props="{}"> </span></li>
</ul>
<ul>
<li data-leveltext="·" data-font="Symbol" data-listid="6" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"·","469777815":"hybridMultilevel"}" data-aria-posinset="2" data-aria-level="1"><span data-contrast="auto">Processor system development, as STM32, with experience in processor interfaces such as Ethernet, PCIe, DDR, FLASH, USB, I2C, SPI, JTAG etc</span><span data-ccp-props="{}"> </span></li>
</ul>
<ul>
<li data-leveltext="·" data-font="Symbol" data-listid="6" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"·","469777815":"hybridMultilevel"}" data-aria-posinset="3" data-aria-level="1"><span data-contrast="auto">Experience in SERDES (eg 112Gbps, PAM4) a benefit</span><span data-ccp-props="{}"> </span></li>
</ul>
<p><span data-ccp-props="{}"> </span></p>
<p><strong><span data-contrast="auto">Other experience required:</span></strong><span data-ccp-props="{}"> </span></p>
<ul>
<li data-leveltext="·" data-font="Symbol" data-listid="6" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"·","469777815":"hybridMultilevel"}" data-aria-posinset="4" data-aria-level="1"><span data-contrast="auto">Demonstrable experience in digital circuit development and validation</span><span data-ccp-props="{}"> </span></li>
</ul>
<ul>
<li data-leveltext="·" data-font="Symbol" data-listid="6" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"·","469777815":"hybridMultilevel"}" data-aria-posinset="5" data-aria-level="1"><span data-contrast="auto">Extensive practical lab experience, bringing up, debugging and validating designs</span><span data-ccp-props="{}"> </span></li>
</ul>
<ul>
<li data-leveltext="·" data-font="Symbol" data-listid="6" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"·","469777815":"hybridMultilevel"}" data-aria-posinset="6" data-aria-level="1"><span data-contrast="auto">Expertise in the use of high-speed digital oscilloscopes, logic analysers and signal generators</span><span data-ccp-props="{}"> </span></li>
</ul>
<ul>
<li data-leveltext="·" data-font="Symbol" data-listid="6" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"·","469777815":"hybridMultilevel"}" data-aria-posinset="7" data-aria-level="1"><span data-contrast="auto">Experience in scripting (Linux, Python, Bash) of tests and Excel to analyse results</span><span data-ccp-props="{}"> </span></li>
</ul>
<ul>
<li data-leveltext="·" data-font="Symbol" data-listid="6" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"·","469777815":"hybridMultilevel"}" data-aria-posinset="8" data-aria-level="1"><span data-contrast="auto">Knowledge of server architecture (BMC, Nic, SSD)</span><span data-ccp-props="{}"> </span></li>
</ul>
<ul>
<li data-leveltext="·" data-font="Symbol" data-listid="6" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"·","469777815":"hybridMultilevel"}" data-aria-posinset="9" data-aria-level="1"><span data-contrast="auto">Autonomy and able to take initiative</span><span data-ccp-props="{}"> </span></li>
</ul>
<ul>
<li data-leveltext="·" data-font="Symbol" data-listid="6" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"·","469777815":"hybridMultilevel"}" data-aria-posinset="10" data-aria-level="1"><span data-contrast="auto">Cross collaboration experience working across different disciplines and people</span><span data-ccp-props="{}"> </span></li>
</ul>
<p><span data-ccp-props="{"335559685":720}"> </span><span data-ccp-props="{}"> </span></p>
<p><strong><span data-contrast="auto">Desirable:</span></strong><span data-ccp-props="{}"> </span></p>
<ul>
<li data-leveltext="·" data-font="Symbol" data-listid="6" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"·","469777815":"hybridMultilevel"}" data-aria-posinset="11" data-aria-level="1"><span data-contrast="auto">Experience of document management and record keeping </span><span data-ccp-props="{}"> </span></li>
</ul>
<ul>
<li data-leveltext="·" data-font="Symbol" data-listid="6" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"·","469777815":"hybridMultilevel"}" data-aria-posinset="12" data-aria-level="1"><span data-contrast="auto">Experience in Mentor (or similar) PCB design flow for schematic capture, design constraints, PCB layout</span><span data-ccp-props="{}"> </span></li>
</ul>
<ul>
<li data-leveltext="·" data-font="Symbol" data-listid="6" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"·","469777815":"hybridMultilevel"}" data-aria-posinset="13" data-aria-level="1"><span data-contrast="auto">Rigorous approach to ensure designs will work correctly first time</span><span data-ccp-props="{}"> </span></li>
</ul>
<ul>
<li data-leveltext="·" data-font="Symbol" data-listid="6" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"·","469777815":"hybridMultilevel"}" data-aria-posinset="14" data-aria-level="1"><span data-contrast="auto">Excellent communications skills with the ability to work both independently and as part of a small team, taking responsibility and willing to participate in all parts of the development cycle</span></li>
</ul>
<p> </p>
<p><strong>What we’ll bring</strong><br><br></p>
<p>In addition to a competitive salary, Graphcore offers flexible working, a generous annual leave policy, private medical insurance and health cash plan, a dental plan, pension (matched up to 5%), life assurance and income protection. We have a generous parental leave policy and an employee assistance programme (which includes health, mental wellbeing, and bereavement support). We offer a range of healthy food and snacks at our central Bristol office and have our own barista bar! We welcome people of different backgrounds and experiences; we’re committed to building an inclusive work environment that makes Graphcore a great home for everyone. We offer an equal opportunity process and understand that there are visible and invisible differences in all of us. We can provide a flexible approach to interview and encourage you to chat to us if you require any reasonable adjustments. </p>
<p><em>Applicants for this position must hold the right to work in the UK. Unfortunately at this time, we are unable to provide visa sponsorship or support for visa applications</em></p>