Cornelis Networks, Inc.: Senior ASIC Ethernet Design Engineer

remote-job.net Job Summary: 💶 Salary: Not provided ⏰ Weekly working hours: Full-time 🔍 Recommended experience: Senior 🎓 Recommended education: Master's degree in Computer Engineering, Computer Science, or Electrical Engineering 🏭 Industry: Semiconductors & HPC/AI Networks 📋 Key responsibilities: End-to-end SoC/ASIC development (specification to delivery). RTL design, design verification, synthesis, and post-silicon validation. Cross-functional collaboration to implement and deliver system solutions. ✅ Key requirements: 15+ years of experience in silicon and ASIC development. 10+ years of experience in network hardware design (50G/100G/400G Ethernet, TCP/IP, RDMA/RoCE, IPSec). Strong proficiency in HDLs (SystemVerilog/Verilog/VHDL) and scripting (TCL/Python/Perl). About the company Cornelis Networks offers high-performance scale-out networking solutions for AI and HPC data centers. The architecture integrates hardware, software, and system technologies to maximize the efficiency of GPU, CPU, and accelerator clusters and accelerate demanding AI and HPC workloads. Backed by leading venture capital and strategic investors, the company focuses on innovation, performance, and scalability. The team consists of architects, engineers, and business professionals working globally across multiple U.S. states and six countries. Cornelis Networks is rapidly growing and filling on-site, hybrid, and fully remote positions. Responsibilities End-to-end development of SoCs/ASICs, including specification and delivery. Front-end standard cell ASIC development: RTL development, design verification, synthesis, and post-silicon validation. Definition, implementation, debugging, and delivery of system solutions focused on purpose-built ASICs. Close cross-functional collaboration with internal and external teams. Requirements At least 15 years of experience in silicon and ASIC development; B.S. in Computer Engineering, Computer Science, or Electrical Engineering (M.S. preferred). 15+ years of experience in digital design with HDLs (SystemVerilog, Verilog, VHDL) and 5+ years of scripting experience (TCL, Python, Perl). 10+ years of relevant experience in network hardware design with proven expertise in 50G/100G/400G Ethernet MAC/PCS, TCP/IP, RDMA/RoCE, and IPSec. Understanding of the standard cell ASIC development flow, including IP integration, simulation, and synthesis; experience with multi-clock designs and asynchronous interfaces is a plus. Benefits Competitive compensation package, including base salary, equity, and performance-based incentives. Comprehensive health benefits: medical, dental, vision, as well as disability and life insurance; additional offerings like pet insurance. Retirement plan with company match (401(k)), family-related benefits, flexible leave model (Open Time Off), paid holidays, and additional leave options (sick leave, parental leave, pregnancy disability). Option for fully remote work within the United States with occasional travel to company offices.